The escalating requirements for high density and performance associated with ultra-large scale integration require increasingly denser arrays with reduced feature sizes. Implementation becomes problematic in manufacturing semiconductor devices having a design rule of about 0.15 micron and under, e.g., about 0.12 micron and under.
Semiconductor devices typically comprise a substrate and elements such as transistors and/or memory cells thereon. Various interconnection layers are formed on the semiconductor substrate to electrically connect these elements to each other and to external circuits. Conventional manufacturing techniques typically comprise forming memory cells in a core memory cell region and forming peripheral circuitry. Processing to form features peculiar to the core memory cell region does not usually correspond or is not necessarily optimal to processing for the peripheral circuitry region. For example, conventional methodology requires the use of at least three separate photoresist masks in the core memory cell region which are removed from the ARC overlying the gate electrode layer in the peripheral circuitry region prior to patterning the gate electrode structure in the peripheral circuitry region. Such conventional methodology requires the formation and removal of different photoresist masks for etching the stacked gate electrode structure, ion implanting impurities to form shallow source/drain extensions and ion implanting impurities to form moderate or heavily doped source/drain implants. These photoresist masks are conventionally removed from the peripheral circuitry region prior to patterning the gate electrode structure of the peripheral circuitry region. However, each time the photoresist is stripped from the ARC, some of the ARC is lost, thereby altering its functional capabilities with respect to avoiding deleterious reflections during photoresist patterning. Consequently, a loss of critical dimension is encountered upon subsequent patterning of the underlying gate electrode structure.
As miniaturization proceeds apace, the loss of dimensional accuracy, including in the peripheral circuitry region, becomes acutely problematic. Accordingly, a need exists for efficient methodology enabling accurate patterning of a gate electrode structure in the peripheral circuitry region, notwithstanding the use of a plurality of masks in the core memory cell region which require stripping.